1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of field effect transistors having a channel region with a specified intrinsic stress to improve the charge carrier mobility.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with a lightly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, substantially depends on the dopant concentration, the mobility of the charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially influences the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, entails a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. In addition, the vertical location of the PN junctions with respect to the gate insulation layer also represents a critical design criterion in view of leakage current control, since reducing the channel length also requires reducing the depth of the drain and source regions with respect to the interface formed by the gate insulation layer and the channel region, thereby requiring sophisticated implantation techniques. According to other approaches, epitaxially grown regions are formed with a specified offset to the gate electrode, which are referred to as raised drain and source regions, to provide increased conductivity of the raised drain and source regions, while at the same time maintaining a shallow PN junction with respect to the gate insulation layer.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates great efforts for the adaptation and possibly the new development of process techniques concerning the above-identified process steps, it has been proposed to also enhance device performance of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length. In principle, at least two mechanisms may be used, in combination or separately, to increase the mobility of the charge carriers in the channel region. First, the dopant concentration within the channel region may be reduced, thereby reducing scattering events for the charge carriers and thus increasing the conductivity. However, reducing the dopant concentration in the channel region significantly affects the threshold voltage of the transistor device, thereby making a reduction of the dopant concentration a less attractive approach unless other mechanisms are developed to adjust a desired threshold voltage. Second, the lattice structure in the channel region may be modified, for instance by creating tensile or compressive strain, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region increases the mobility of electrons, wherein, depending on the magnitude of the tensile strain, an increase in mobility of up to 120% may be obtained, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
Therefore, in some conventional approaches, for instance, a silicon/germanium layer or a silicon/carbon layer is provided in or below the channel region to create tensile or compressive strain therein. Although the transistor performance may be considerably enhanced by the introduction of strain-creating layers in or below the channel region, significant efforts have to be made to implement the formation of corresponding layers into the conventional and well-approved CMOS technique. For instance, additional epitaxial growth techniques have to be developed and implemented into the process flow to form the germanium- or carbon-containing stress layers at appropriate locations in or below the channel region. Hence, process complexity is significantly increased, thereby also increasing production costs and the potential for a reduction in production yield.
In other approaches, stress from an etch stop layer that is required on top of the transistors to control a contact etch process is used to induce strain in the channel regions of the transistors, wherein compressive strain is created in the P-channel transistor, while tensile strain is created in the N-channel transistor. However, this conventional approach, although offering substantial performance advantages, may bring about some drawbacks that may partially offset the benefits accomplished by the enhanced strain engineering, as will be described with reference to FIGS. 1a-1d. 
FIG. 1a schematically shows a cross-sectional view of a semiconductor device 150 comprising an NMOS transistor element 100n and a PMOS transistor element 100p. The transistor elements 100n, 100p may be provided in the form of silicon-on-insulator (SOI) devices. Thus, the semiconductor device 150 comprises a silicon substrate 101 having formed thereon an insulating layer 102, such as a buried silicon dioxide layer, followed by a crystalline silicon layer 103. The transistors 100n, 100p may be separated from each other by an isolation structure 120, for instance in the form of a shallow trench isolation. The transistor 100n further comprises a gate electrode structure 105 including a polysilicon portion 106 and a metal silicide portion 108. The gate electrode structure 105 further comprises a gate insulation layer 107 separating the gate electrode structure 105 from a channel region 104, which, in turn, laterally separates appropriately doped source and drain regions 111 having formed therein metal silicide regions 112. A spacer element 110 is formed adjacent the sidewalls of the gate electrode structure 105 and is separated therefrom by a liner 109, which is also formed between the source and drain regions 111 and the spacer element 110. In some cases, the liner 109 may be omitted.
The second transistor 100p may have substantially the same configuration and the same components, wherein the channel region 104 and the drain and source regions 111 include different dopants compared to the respective regions of the transistor 100n. 
A typical process flow for forming the semiconductor device 150 as shown in FIG. 1a may comprise the following processes. The substrate 101, the insulating layer 102 and the silicon layer 103 may be formed by advanced wafer bond techniques when the semiconductor device 150 is to represent an SOI device, or the substrate 101 may be provided without the insulating layer 102, as a bulk semiconductor substrate, wherein the silicon layer 103 may represent an upper portion of the substrate, or may be formed by epitaxial growth techniques. Thereafter, the gate insulation layer 107 may be deposited and/or formed by oxidation in accordance with well-established process techniques followed by the deposition of polysilicon by means of low pressure chemical vapor deposition (CVD). Thereafter, the polysilicon and the gate insulation layer 107 may be patterned by sophisticated photolithography and etch techniques in accordance with well-established process recipes. Next, implantation cycles in combination with the manufacturing process for forming the spacer element 110 may be performed, wherein the spacer element 110 may be formed as two or more different spacer elements with intermediate implantation processes when a sophisticated laterally profiled dopant concentration is required for the drain and source regions 111. For example, extension regions 114 of reduced penetration depth may be required. After any anneal cycles for activating and partially curing implantation-induced crystal damage, the metal silicide regions 108 and 112 are formed by depositing a refractory metal and initiating a chemical reaction with the underlying silicon, wherein the spacer element 110 acts as a reaction mask for preventing or reducing the formation of the metal compound between the gate electrode structure 105 and the drain and source regions 111.
FIG. 1b schematically shows the semiconductor device 150 with an etch stop layer 116 and a liner 117 formed above the transistor elements 100n and 100p. Typically, the transistor elements 100n, 100p are embedded in an interlayer dielectric material (not shown in FIG. 1B) over which corresponding metallization layers are to be formed to establish the required electrical connections between the individual circuit elements. The interlayer dielectric material has to be patterned to provide contacts to the gate electrode structure 105 and the drain and source regions 111 by means of an anisotropic etch process. Since this anisotropic etch process has to be performed to different depths, a reliable etch stop layer is provided to prevent a material removal at the gate electrode structure 105 when the etch front has reached the gate electrode structure 105 and still continues to approach the drain and source regions 111. Frequently, the interlayer dielectric material is comprised of silicon dioxide and thus the etch stop layer 116 may comprise silicon nitride, as silicon nitride exhibits a good etch selectivity for well-established anisotropic process recipes for etching silicon dioxide. In particular, silicon nitride may be deposited in accordance with well-established deposition recipes, wherein the deposition parameters may be adjusted to provide a specified intrinsic mechanical stress while at the same time still maintaining the desired high etch selectivity to silicon dioxide. Typically, silicon nitride is deposited by plasma enhanced chemical vapor deposition (PECVD), wherein, for example, parameters of the plasma atmosphere, such as the bias power supplied to the plasma atmosphere, may be varied to adjust the mechanical stress created in the silicon nitride layer as deposited. For example, the deposition may be performed by well-established process recipes on the basis of silane (SiH4) and ammonia (NH3), nitrogen oxide (N2O) or nitrogen (N2) in a deposition tool for PECVD for a silicon nitride layer. The stress in the silicon nitride layer may be determined by the deposition conditions, wherein, for instance, a compressive stress in silicon nitride of up to approximately 1 GPa (Giga-Pascal) may be obtained with a moderately high bias power according to well-established deposition recipes, while in other embodiments a tensile stress of up to approximately 1 GPa may be achieved by reducing the ion bombardment caused by the bias power in the deposition atmosphere.
Hence, in a conventional approach, the etch stop layer 116 is deposited as a silicon nitride layer having a specified compressive stress. Thereafter, the liner 117 is deposited as a silicon dioxide layer by well-established PECVD techniques.
FIG. 1c schematically shows the semiconductor device 150 with a resist mask 140 formed above the transistor element 100n, 100p to cover the transistor 100p and to expose the transistor 100n. Moreover, the semiconductor device 150 is subjected to an etch process 160 for removing those portions of the etch stop layer 116 and the liner 117 that are not covered by the resist mask 140. For example, the etch process 160 may comprise a first etch step for removing silicon dioxide followed by an etch step to remove silicon nitride. During the etch process 160, the metal silicide portions 108, 112 are exposed to the reactive etch atmosphere, which may result in damage and/or material removal from these regions. Moreover, the regions 108, 112 may also be exposed to a reactive ambience during subsequent clean processes as are typically performed prior to the further processing of the device 150.
FIG. 1d schematically shows the semiconductor device 150 in a further advanced manufacturing stage, wherein a second etch stop layer 119 comprised of silicon nitride and having intrinsic tensile stress is formed above the transistor elements 100n, 100p. Moreover, a further resist mask 170 is formed above the device 150 to expose the transistor 100p while covering the transistor 100n. Furthermore, the device 150 is subjected to an etch process 180 for removing the exposed portion of the second etch stop layer 119 and the remaining liner 117.
Consequently, after completion of the above-described process flow, the transistor 100p comprises an etch stop layer having intrinsic compressive stress that induces a respective compressive strain within the channel region 104, while the transistor 100n has formed thereon the etch stop layer 119 having the intrinsic tensile stress, thereby creating tensile strain in the respective channel region 104. However, owing to the etch process 160 and any further cleaning processes performed after the etch process 160, a significant degradation of the regions 108, 112 of the transistor 100n may have resulted and thus may significantly deteriorate the overall performance of the transistor 100n, thereby partially offsetting the advantages achieved by the enhanced strain engineering described above.
In view of the above-described situation, there exists a need for an alternative technique that enables the creation of different strain in different transistor elements while substantially avoiding or at least reducing at least some of the problems identified above.